This invention relates to control of clock signal operation, and more particularly to, a clock signal control device to prevent the wrong operation of system due to unstable operation of clock signal that may occur when the power supply of an electronic device, such as a portable terminal, is turned on.
In an information storage device driven by AC power supply, such as a desktop personal computer, data necessary to the application program are stored into storage, such as hard disk. Thus, even when power supply to the information storage device is turned off, no data is lost. However, in a portable information storage device driven by dry cell, a hard disk that consumes too much power cannot be used.
Therefore, a non-volatile memory device, such as EEPROM or flash memory, is used therein to retain data. Also there are devices that turn off the power supply after data are stored into memory. However, the non-volatile memory devices are generally expensive, considering the cost per memory capacity. Thus a self-refresh type device, a volatile memory such as DRAM, is commonly used. In a unit using a DRAM type device, the clock signal is stopped to end the signal change of the device, while still supplying power. Thereby, the power off state is built.
Also, even in a unit where the content of memory is not necessary to retain, there may occur the case that power supply to the unit needs to be turned off while retaining the state of signal in respective circuits of the unit. For such a case, supplying of the clock signal to the unit is stopped to end the operation of the device, while supplying power. Thereby, the power OFF state of the unit is built.
In any case, to build the power OFF state, power supplying to an oscillator as oscillation source is ended to stop the clock signal.
However, when the operation again starts after stopping the clock signal, the clock signal may become unstable, as the case may be, causing the wrong operation and coming to failure in the unit operation. So, it is necessary to avoid the wrong operation due to the clock signal to restart stably the unit.
Japanese patent application laid-open Nos. 62-86419 (1987) and 4-25958 (1992) (hereinafter referred to as xe2x80x98prior art 1xe2x80x99 and xe2x80x98prior art 2xe2x80x99, respectively) disclose a system using CPU that operates synchronizing with the clock signal. In this system, the start of operation is delayed by a delay buffer after turning on the power supply, and the system operation starts after the clock signal becomes stable. Thereby, the wrong operation when turning on the power supply is turned on can be avoided.
Japanese patent application laid-open No. 6-101452 (1994) (hereinafter referred to as xe2x80x98prior art 3xe2x80x99) disclose a method where the oscillation of oscillator is counted until the clock signal is stabilized, in order to avoid the wrong operation due to unstable clock signal when turning on the power supply. By thus keeping the system suspended until counting a given value, the wrong operation due to unstable clock signal when turning on the power supply can be avoided.
Also, Japanese patent application laid-open No. 8-316832 (1996) (hereinafter referred to as xe2x80x98prior art 4xe2x80x99) discloses a method where a D flip-flop, instead of a capacitor, is used to detect the locking state of a PLL circuit to generate a clock signal to be supplied to semiconductor integrated circuit.
Japanese patent application laid-open No. 3-165617 (1996) (hereinafter referred to as xe2x80x98prior art 5xe2x80x99) discloses a method where the pseudo-clock signal is generated by a CR oscillator only at the initial stage so as to not get the operation clock signal in the unstable stage of oscillation, e.g., when turning on the power supply.
Japanese patent application laid-open No. 3-165619 (1996) (hereinafter referred to as xe2x80x98prior art 6xe2x80x99) discloses a method where for the purpose of solving the wrong operation of system due to unstable operation of clock signal at the initial stage, e.g., when turning on the power supply, the circuit is operated using the output of CR oscillator, which has a faster oscillation-starting time than a quartz oscillator, until the oscillation of the quartz oscillator as a true system clock signal starts. Detecting the time when the quartz oscillator starts to oscillate, the clock signal to be supplied to the system is replaced by the output of the quartz oscillator.
Japanese patent application laid-open No.9-134593 (1997) (hereinafter referred to as xe2x80x98prior art 7xe2x80x99) discloses a method where there are disposed several flip-flops thereby initialization signal is output when several clock pulses are input.
The problems of the above prior arts 1 to 7 are as follows: Prior arts 1 and 2 employ the method that the start timing of system operation is delayed by a few counts of clock signal by the counter. Thus, the clock signal is also supplied to the counter to count the amount of delay. Therefore, the counter taking a timing when turning on the power supply or when restarting the operation from the suspended state of clock signal may also be influenced by the unstable state of clock signal operation, thereby running into the wrong operation.
In prior art 3, like the cases of prior arts 1 and 2, a reset signal to be input to the system is generated by using the counter and the operation of the circuit is delayed by this reset signal during a certain period. Thus, by keeping the circuit suspended during the unstable period of oscillator such as just after turning on the power supply, the wrong operation is prevented. However, in this system, the clock signal of the oscillator is supplied to the counter to make the delay, the counter may run into the wrong operation during the unstable period of oscillator such as just after turning on the power supply.
In prior art 4, a reference frequency circuit is used to detect the locking of PLL. The reference frequency circuit necessary for the frequency locking of PLL needs to have stabilized oscillation before the oscillator that supplies the clock signal starts to oscillate. Therefore, the reference frequency circuit needs to be continuously oscillating, or to start to oscillate before the oscillator that supplies the clock signal starts to oscillate such that it is already oscillating when the oscillator starts to oscillate. Also, to check the frequency locking by phase comparison, a further circuit such as a phase comparator or VCO is necessary. Thus, there is the problem that the entire circuit is complicated.
In prior arts 5 and 6, an oscillator, which has a faster oscillation-starting timing than the actually-used oscillator, is used at the initial stage of operation, and when the oscillation of the actually-used oscillator becomes stable, the system is operated replacing the initial-stage oscillator by the actually-used oscillator. However, even when the initial-stage oscillator has a faster oscillation-starting timing than the quartz oscillator, it may be unstable when turning on the power supply. Eventually, there still exists the problem that the wrong operation of circuit can occur when turning on the power supply.
Accordingly, it is an object of the invention to provide a clock signal control device by which a system can surely start the stable operation when it restarts.
It is a further object of the invention to provide a clock signal control device that has a simplified circuit composition advantageous to high integration, as well as the stability when restarting the system.
It is a still further object to provide a clock signal control device with a simplified circuit composition that can avoid the wrong operation of circuit due to unstable operation of clock signal when turning on the power supply.
According to the invention, a clock signal control device, comprising:
an oscillator which generates a clock signal;
a pulse detecting circuit which detects the frequency or duty of the clock signal and outputs a control signal based on the result of detection; and
a clock signal supply selecting circuit which generates a supply clock signal from the clock signal generated from the oscillator in response to the control signal from the pulse detecting circuit.